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MIPS CPU in Verilog

[View Source Code on Github]

This is a CPU design I did for CSCE 611 Advanced Digital Design. It was originally designed for a Cyclone IV FPGA with VGA output, but the repo also includes C++ files for running Verilator simulations with an SDL frontend. The simulation is extremely slow, however. If you would still like to run it, you can test it with:

$ git clone https://github.com/NighttimeDriver50000/mips_cpu_611.git
$ cd mips_cpu_611
$ ./tool/make.sh
$ ./obj_dir/Vmips_cpu_inst_for_sdl

This is probably all I’ll do on getting this to run on Verilator, seeing as the simulation is so slow. The code is MIT licensed, but there are far better MIPS CPUs out there.


© Emberlynn McKinney